AT87251G2D-3CSUM【PDF 4/77 页】IC 8051 MCU 32K OTP 24MHZ 40DIP

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AT/TSC8x251G2D

4135F–8051–11/06

compatibility with the C51 Architecture). When PC increments beyond the end of seg-

ment FE:, it continues at the reset address FF:0000h (linearity). When PC increments

beyond the end of segment 01:, it loops to the beginning of segment 00: (this prevents

from its going into the reserved area).

Data Memory

The TSC80251G2D derivatives implement 1 Kbyte of on-chip data RAM. Figure 5

shows the split of the internal and external data memory spaces. This memory is

mapped in the data space just over the 32 bytes of registers area (see TSC80251 Pro-

grammers’ Guide). Hence, the part of the on-chip RAM located from 20h to FFh is bit

addressable. This on-chip RAM is not accessible through the program/code memory

space.

F o r f a st er com put atio n w i th t he on- chip R O M / EPR O M cod e o f the

TSC83251G2D/TSC87251G2D, its upper 16 KB are also mapped in the upper part of

the region 00: if the On-Chip Code Memory Map configuration bit is cleared (EMAP# bit

in UCONFIG1 byte, see Figure ). However, if EA# is tied to a low level, the

TSC80251G2D derivative is running as a ROMless product and the code is actually

fetched in the corresponding external memory (i.e. the upper 16 KB of the lower 32 KB

of the segment FF:). If EMAP# bit is set, the on-chip ROM is not accessible through the

region 00:.

All the accesses to the portion of the data space with no on-chip memory mapped onto

are redirected to the external memory.

Figure 5.

Data Memory Mapping

On-chip ROM/EPROM

Code Memory

Data Segments

Data External

Memory Space

16 KB

EA# = 0

EA# = 1

32 KB

Reserved

64 KB

47 KB

FF:FFFFh

FF:8000h

FF:7FFFh

FF:0000h

FE:FFFFh

FE:0000h

FD:FFFFh

01:FFFFh

01:0000h

02:0000h

00:FFFFh

00:0420h

32 bytes reg.

RAM Data

1 Kbyte

16 KB

00:C000h

00:BFFFh

EMAP# = 1

EMAP# = 0

16 KB

64 KB

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